A Novel Architecture for Floating-Point Multiply-Add-Fused Operation with Reduced Latency

The multiply-add-fused (MAF) operation is very important in many scientific and engineering applications. In this paper, a novel architecture for the MAF operation is presented. According to the fact that some steps of MAF operation are mutually exclusive, the composing steps are organized into two data-paths, and each data-path only contains the indispensable computation steps. One takes effect when the effective subtraction occurs, and the other takes effect when the effective subtraction does not occur. The difference between execution time of the two datapaths is one beat, so the average latency is shortened. Furthermore, the dual adder combined with rounding is invoked by the two data-paths in different beats, therefore it may be shared by the two data-paths and the circuit area may be saved.